State assignment for multilevel logic using dynamic literal estimation

The problem of assigning a representation for the states in a finite-state machine (FSM) so as to minimize the area required for implementation using multilevel logic is considered. The problem is reduced to one of minimizing the literal count in the combinational logic part of the FSM. Heuristics are used to guide the selection of candidate state assignments, and a fast literal estimator is used to choose the best assignment from among the candidates. This approach is compared to the mustang program and is found to produce, on average, smaller literal counts than mustang.<>