Title :
Automated synthesis of asynchronous pipelines
Author :
Kuo, Yau-Hwang ; Lo, Shaw-Pyng
Author_Institution :
Inst. of Inf. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan
Abstract :
Proposes a system for the automatic synthesis of asynchronous pipelines. A high-level hardware description language (HDL) called Masil-II is developed to describe the circuit behavior at algorithmic level. A modified Petri net is used as intermediate description. From the intermediate description, several techniques such as clique partitioning, simulated evolution, and heuristics are applied to realize the data path synthesis task. Experimental results have confirmed their efficiency
Keywords :
Petri nets; VLSI; logic CAD; pipeline processing; specification languages; Masil-II; asynchronous pipelines; circuit behavior; clique partitioning; data path synthesis task; hardware description language; heuristics; intermediate description; modified Petri net; simulated evolution; Circuit simulation; Circuit synthesis; Clocks; Delay; Hardware design languages; Integrated circuit interconnections; Partitioning algorithms; Pipelines; Resource management; System recovery;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230159
