An approach for the yield enhancement of programmable gate arrays

Author

Kumar, V. ; Dahbura, A. ; Fischer, F. ; Juola, P.

Author_Institution

AT&T Bell Lab., Holmdel, NJ, USA

fYear

1989

fDate

5-9 Nov. 1989

Firstpage

226

Lastpage

229

Abstract

Programmable gate arrays (PGAs) offer a convenient means of prototyping complex logic. An approach is presented for enhancing the yield of PGAs through defect tolerance. This serves two purposes: to make the product economical, as well as to help reduce the turnaround time. The approach is based on using programmable interconnect to test the logic in the PGA and to use adaptive customization to avoid the defective portions. The ideas are illustrated through the use of a novel PGA architecture. Heuristics for adaptive customization of the PGAs are given and their effectiveness is studied through yield analysis. The results of the study for a sample circuit are included.<>

Keywords

logic CAD; logic arrays; adaptive customization; architecture; complex logic; defect tolerance; heuristics; programmable gate arrays; programmable interconnect; prototyping; turnaround time; yield analysis; yield enhancement; Electronics packaging; Fuses; Integrated circuit interconnections; Logic circuits; Logic devices; Logic gates; Logic programming; Logic testing; Programmable logic arrays; Prototypes;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-1986-4

Type

conf

DOI

10.1109/ICCAD.1989.76941

Filename

76941