An efficient approach to pipeline scheme for concurrent testing of VLSI circuits

Presents a unifying procedure, called implicit tree search algorithm (ITSA), for automated allocation of test events in a pipeline scheme for concurrent testing of VLSI circuits. The procedure fully exploits the test parallelism where the test intervals of compatible test events are overlaid so that the system can test as many of them as possible concurrently. Moreover, the utilization of BIST (built-in self-test) resources is optimized. The operation of the ITSA is clearly demonstrated with the detailed examples provided. The simulation shows that ITSA is efficient and generates the scheduling results better than previous work