Title :
Proceedings. 6th international symposium on quality electronic design
Abstract :
The following topics are dealt with: tools and flows for quality design; high level power/noise reduction techniques; leakage and dynamic power issues; test application and cost reduction; DFM and physical layout; performance and reliability analysis for yield optimization; functional verification and test generation; power delivery and distribution; quality system level design and synthesis; DFM for circuit design; leakage and reliability management; analog test and BIST; nanoelectronics: evolution or revolution; design methods and tools in DSM; design techniques for leakage reduction; variability issues in nanoscale circuits; issues in noise and timing; design approaches for system in package (SIP); DSM interconnect issues; advances in floorplanning; issues in on-chip communication and analog/RF designs; and robust design under parameter variations.
Keywords :
automatic test pattern generation; built-in self test; circuit layout; circuit optimisation; design for manufacture; distributed shared memory systems; electronics packaging; integrated circuit yield; nanoelectronics; performance evaluation; power consumption; system-on-chip; BIST; DFM; DSM; SIP; analog test; circuit design; cost reduction; floorplanning; functional verification; leakage reduction; nanoelectronics; noise reduction; performance; physical layout; power delivery; power reduction; quality system level design; reliability analysis; system in package; test generation; yield optimization;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Conference_Location :
San Jose, CA, USA
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.124
