Title :
Inserting active delay elements to achieve wave pipelining
Author :
Wong, D. ; De Micheli, G. ; Flynn, M.
Author_Institution :
Dept. of Electr. Eng., Stanford Univ., CA, USA
Abstract :
Wave pipelining is a technique for pipelining digital systems that can increase the clock frequency without increasing the number of storage elements. Due to limits and variations in fabrication, the clock frequency can be increased by a factor of 2 to 3 by using the best available design methods. The authors present algorithms that will equalize delays automatically by inserting a minimal number of active delay elements to lengthen short paths. This method can be combined with delay balancing by adjusting gate speeds to design wave-pipelined circuits.<>
Keywords :
circuit CAD; active delay elements; clock frequency; delay balancing; digital systems; gate speeds; wave pipelining; Circuit optimization; Clocks; Combinational circuits; Feedback circuits; Logic design; Pipeline processing; Propagation delay; Registers; Temperature; Tuned circuits;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76951
