A new approach to optimal cell synthesis

Author

Madsen, J.

Author_Institution

DesignCenter of Electron. Inst., Tech. Univ. of Denmark, Lyngby, Denmark

fYear

1989

fDate

5-9 Nov. 1989

Firstpage

336

Lastpage

339

Abstract

A set of algorithms is presented for optimal layout generation of CMOS complex gates. The algorithms are able to handle global physical constraints, such as pin placement, and to capture timing aspects. Results show that this novel approach provides better solutions in area and speed compared t other methods. The algorithms have been implemented in a cell compiler (CELLO) working in an experimental silicon compiler environment.<>

Keywords

CMOS integrated circuits; circuit layout CAD; logic CAD; CELLO; CMOS complex gates; cell compiler; global physical constraints; optimal cell synthesis; optimal layout generation; pin placement; silicon compiler environment; timing aspects; Algorithm design and analysis; Circuit optimization; Design optimization; Propagation delay; Routing; Silicon compiler; Timing;

fLanguage

English

Publisher

ieee

Conference_Titel

Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on

Conference_Location

Santa Clara, CA, USA

Print_ISBN

0-8186-1986-4

Type

conf

DOI

10.1109/ICCAD.1989.76965

Filename

76965

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=2855460