Title :
CLEO: a CMOS layout generator
Author :
Domic, A. ; Levitin, S. ; Phillips, N. ; Thai, C. ; Shiple, T. ; Bhavsar, D. ; Bissel, C.
Author_Institution :
Digital Equipment Corp., Hudson, MA, USA
Abstract :
A description is given of CLEO, an automatic CMOS layout generator that takes as input an arbitrary sized circuit schematic and produces a CMOS layout as one or more horizontal rows of vertically oriented transistors. The layout can be controlled by specifying geometric constraints such as the number of rows desired, their specific heights and widths, and pins located on the region boundary. The tool was designed to lay out random logic sections of custom CMOS chips and is typically used with circuits ranging between 25 and 500 logic gates. CLEO obtains density close to handcrafted layout.<>
Keywords :
CMOS integrated circuits; circuit layout CAD; CLEO; CMOS layout generator; arbitrary sized circuit schematic; custom CMOS chips; geometric constraints; vertically oriented transistors; Automatic control; CMOS logic circuits; Geometry; Libraries; Logic design; Logic gates; Pins; Production; Productivity; Routing;
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
DOI :
10.1109/ICCAD.1989.76966
