An architecture for real time processing of SAR signals

A time-domain architecture for real-time processing of SAR (synthetic aperture radar) data using lower data rates and dedicated hardware is discussed. The architecture uses a novel correlator for processing range and azimuth data. In compressing the range correlated data in the azimuth direction, no explicit range migration correction is employed. A data reduction rate of 8 is achieved in the presummer circuit, which enables real-time processing with moderately high-speed multipliers. With high speed multipliers and lower data rates, images like those from Seasat can be processed in real time. For the data rates proposed, multipliers operating at 6.25 MFLOPS are sufficient. Since the architecture uses CMOS VLSI chips and a minimum amount of memory, the size and power consumption are expected to be low and hence ideally suited for spaceborne applications