DocumentCode
2855584
Title
FACT-a testability analysis methodology
Author
Sridhar, T.
Author_Institution
Gateway Design Autom. Corp., Lowell, MA, USA
fYear
1989
fDate
5-9 Nov. 1989
Firstpage
366
Lastpage
369
Abstract
A novel approach, called FACT (fault analysis and critique technique), that can provide facts about untestable and difficult-to-test faults in sequential designs by identifying them in a deterministic way is proposed. The importance of identifying such faults early in the design cycle is discussed, along with their effect on computer execution time, increasing it by as much as 65%, during test generation and simulation. These are demonstrated with real examples. Details of the underlying concepts used in FACT are explained. Some experimental results are presented.<>
Keywords
logic CAD; logic testing; FACT; difficult-to-test faults; fault analysis; sequential designs; testability analysis; Automatic test pattern generation; Automatic testing; Circuit faults; Circuit testing; Computational modeling; Design automation; Design for testability; Fault diagnosis; Manufacturing automation; Runtime;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location
Santa Clara, CA, USA
Print_ISBN
0-8186-1986-4
Type
conf
DOI
10.1109/ICCAD.1989.76971
Filename
76971
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