DocumentCode
2855758
Title
500-MHz clock-rate logic LSI
Author
Fujioka, A. ; Taniguchi, Kazuhiro ; Hayasaka, A. ; Matsui, K. ; Yumoto, O. ; Sakai, Kenji
Author_Institution
Hitachi Central Research Laboratory, Tokyo, Japan
Volume
XVI
fYear
1973
fDate
14-16 Feb. 1973
Firstpage
164
Lastpage
165
Abstract
The development of 500-MHz clock rate logic LSIs, with a wide operating range, will be discussed, citing a proposed 1-GHz flip-flop operating stably as a master-slave flip flop.
Keywords
Clocks; Crosstalk; Delay effects; Flip-flops; Interference; Large scale integration; Logic circuits; Propagation delay; Space vector pulse width modulation; Timing;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1973 IEEE International
Conference_Location
Philadelphia, PA, USA
Type
conf
DOI
10.1109/ISSCC.1973.1155205
Filename
1155205
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