DocumentCode :
2855796
Title :
Technology mapping for reliability enhancement in logic synthesis
Author :
Wo, Zhaojun ; Koren, Israel
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
fYear :
2005
fDate :
21-23 March 2005
Firstpage :
137
Lastpage :
142
Abstract :
Reliability enhancements are traditionally implemented through redundancies at the system level or through the use of harden-cell-designs at the circuit level. Reliability is commonly ignored during the logic synthesis step. A major reason for this is the fact that constructing a cost function to measure sensitivity to faults at the logic synthesis level is complex. The work presented in this paper addresses one important aspect of synthesis for high reliability. It focuses on the problem of mapping a technology independent circuit to a technology specific one, using gates from a given library, with fault sensitivity as an optimization metric. We believe that the difficulty in obtaining accurate metrics of fault sensitivity at the technology independent level makes it hard to optimize at this level, thus technology dependent mapping offers a direct method to improve reliability. In this paper, we present a concept named "effective fault area" for mapping onto library gates. Along with this concept, we adopt a Markov-model based analytical method to accurately estimate fault sensitivity during mapping with a low computational overhead. Several benchmark results show that the average reliability improvement is about 20.7% at the cost of 12.1% increase in delay.
Keywords :
Markov processes; circuit optimisation; circuit reliability; logic CAD; logic gates; logic testing; Markov-model based analytical method; effective fault area; fault sensitivity; gate library; logic synthesis; optimization; reliability enhancement; technology mapping; Circuit faults; Circuit synthesis; Cost function; Delay; Digital systems; Latches; Libraries; Logic devices; Neutrons; Redundancy;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
Type :
conf
DOI :
10.1109/ISQED.2005.118
Filename :
1410572
Link To Document :
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