DocumentCode :
2855832
Title :
HAM-a hardware accelerator for multi-layer wire routing
Author :
Venkateswaran, R. ; Mazumder, P.
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Michigan Univ., Ann Arbor, MI, USA
fYear :
1989
fDate :
5-9 Nov. 1989
Firstpage :
440
Lastpage :
443
Abstract :
The authors investigate a C-wrapped hexagonal mesh architecture (called HAM, for hexagonal array machine) for the physical implementation of the Lee algorithm. They show the high promise of such a machine in handling routing on single as well as on multiple layers. The mapping corresponding to a C-wrapped hexagonal interconnection of N processing elements (PEs) results in an interprocessor cycle length of N. This is much superior to the N/2 results obtained by other researchers. Consequently, fewer conflicts arise during wave-front expansion and a good quality routing can be achieved in a much shorter period. The authors show that a hexagonal mesh with 3 kG PEs can do routing on k-layer grids with kG/sup 2/ grid points at speeds comparable to the full grid machine.<>
Keywords :
circuit layout CAD; parallel architectures; parallel machines; printed circuit design; C-wrapped hexagonal interconnection; C-wrapped hexagonal mesh architecture; Lee algorithm; hardware accelerator; hexagonal array machine; interprocessor cycle length; multi-layer wire routing; wave-front expansion; Circuit faults; Circuit topology; Hardware; Integrated circuit interconnections; Integrated circuit layout; Printed circuits; Routing; Very large scale integration; Wire; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Computer-Aided Design, 1989. ICCAD-89. Digest of Technical Papers., 1989 IEEE International Conference on
Conference_Location :
Santa Clara, CA, USA
Print_ISBN :
0-8186-1986-4
Type :
conf
DOI :
10.1109/ICCAD.1989.76987
Filename :
76987
Link To Document :
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