DocumentCode :
285591
Title :
A study of the use of local interconnect in CMOS leaf cell design
Author :
Bachelu, C.R. ; Lefebvre, M.C.
Author_Institution :
Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada
Volume :
3
fYear :
1992
fDate :
10-13 May 1992
Firstpage :
1258
Abstract :
The authors present a leaf-cell layout methodology for harnessing the potential of the local interconnect (LI) layer in digital CMOS circuits. Based on the line-of-diffusion layout style, LI is used for selected connections, typically at the output of logic gates, in order to free up the metal layer in congested areas. The authors present experimental results based on a variety of logic cells which demonstrate the benefit of the LI in terms of cell area, circuit reliability, and routing flexibility
Keywords :
CMOS integrated circuits; circuit layout; digital integrated circuits; integrated circuit technology; cell area; circuit reliability; digital CMOS circuits; layout methodology; leaf cell design; line-of-diffusion; local interconnect; logic gates; routing flexibility; CMOS digital integrated circuits; CMOS logic circuits; CMOS technology; Fabrication; Flexible printed circuits; Integrated circuit interconnections; Logic gates; Routing; Signal processing; Titanium;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
Type :
conf
DOI :
10.1109/ISCAS.1992.230277
Filename :
230277
Link To Document :
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