Title :
Reliability driven logic synthesis of multilevel circuits
Author :
De, Kaushik ; Wu, Chienwen ; Banerjee, Prithviraj
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
Two schemes for reliability-driven logic synthesis of multilevel circuits are presented. Previous schemes of duplications required 100% area overhead. The first scheme uses the Berger code for concurrent error detection for the multilevel circuits. The average area overhead is 22% in this scheme. The second scheme uses the output partitioning and parity prediction method. It is found that the average area overhead of this scheme is about 67%
Keywords :
circuit reliability; error detection; integrated logic circuits; logic design; many-valued logics; Berger code; area overhead; concurrent error detection; multilevel circuits; output partitioning; parity prediction; reliability-driven logic synthesis; Circuit faults; Circuit synthesis; Circuit testing; Combinational circuits; Electrical fault detection; Fault detection; Logic circuits; Logic testing; Programmable logic arrays; Very large scale integration;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230286
