DocumentCode :
285603
Title :
A novel double-decomposition method for systolic implementation of DFT
Author :
Wang, L. ; Hartimo, I. ; Laakso, T.
Author_Institution :
Helsinki Univ. of Technol., Espoo, Finland
Volume :
3
fYear :
1992
fDate :
10-13 May 1992
Firstpage :
1085
Abstract :
The authors discuss a novel systolic implementation of the discrete Fourier transform (DFT) algorithm by using a novel double-decomposition method to create two 4-point systolic preprocessors for a direct linear DFT implementation. The approach is well suited for large DFTs and reduces the number of required processors very effectively. The decomposition is carried out in two phases, first in the frequency and then in the time domain. With this double-decomposition, an N-point DFT can be implemented using sixteen N/16-point DFTs. A corresponding fully pipelined word-level systolic implementation is developed with time complexity O(N), in which only N/16+4 systolic processors are used in addition to 24 complex adders, three real adders, and five real multipliers. The elements of the systolic processors are of CORDIC (coordinate rotation digital computer)-type
Keywords :
digital arithmetic; digital signal processing chips; fast Fourier transforms; parallel algorithms; pipeline processing; signal processing; systolic arrays; 4-point systolic preprocessors; CORDIC; DFT; DSP; FFT; coordinate rotation digital computer; discrete Fourier transform; double-decomposition method; frequency domain; fully pipelined word-level; systolic implementation; time domain; Digital signal processing; Discrete Fourier transforms; Frequency domain analysis; Hardware; Pipelines; Signal processing algorithms; Systolic arrays; Throughput; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
Type :
conf
DOI :
10.1109/ISCAS.1992.230291
Filename :
230291
Link To Document :
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