Title :
Using MUXs network to hide bunches of scan chains
Author :
Han, Yinhe ; Hu, Yu ; Li, Huawei ; Li, Xiaowei
Author_Institution :
Inst. of Comput. Technol., Acad. Sinica, Beijing, China
Abstract :
This paper presents a decompression architecture using a periodically alterable MUX network. Compared to the static XOR network, the periodically alterable MUX network has multiple configurations to decode the input information flexibly. Probability analysis can help us to select the proper parameter when considering the DFT schemes. With the dedicated efforts, smaller test data volume and test application time can be achieved compared to previous techniques.
Keywords :
design for testability; industrial property; integrated circuit testing; probability; system-on-chip; DFT schemes; IP cores; SoC; decompression architecture; intellectual property; periodically alterable MUX network; probability analysis; scan chain bunches; test application time; Circuit testing; Compaction; Computer architecture; Decoding; Electronic mail; Feeds; Genetic mutations; Intellectual property; Logic testing; Ring generators;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.127
