Title :
DVFS Aware Techniques on Parallel Architecture Core (PAC) Platform
Author :
Tseng, Shau-Yin ; Chang, Ming-Wei
Author_Institution :
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu
Abstract :
Rapid developments of multimedia and communication technologies enrich the applications of portable devices. However, design flexibility and low power are two important criteria for real-time system development. In this paper, a DVFS-aware implementation is introduced to demonstrate intelligent dynamic voltage and frequency scaling (DVFS) technique on dual-core PAC Platform. The power management of DVFS technique is verified with the H.264/AVC decoder example which can save 46% of power consumption.
Keywords :
parallel architectures; power aware computing; video codecs; DVFS aware techniques; H.264/AVC decoder; intelligent dynamic voltage and frequency scaling technique; parallel architecture core platform; portable devices; power management; real-time system development; Automatic voltage control; Communications technology; Decoding; Dynamic voltage scaling; Energy management; Frequency; Multimedia communication; Parallel architectures; Power system management; Real time systems; Clock gating; H.264 decoder; dynamic voltage scaling;
Conference_Titel :
Embedded Software and Systems Symposia, 2008. ICESS Symposia '08. International Conference on
Conference_Location :
Sichuan
Print_ISBN :
978-0-7695-3288-2
DOI :
10.1109/ICESS.Symposia.2008.87
