Program Compression Based on Arithmetic Coding on Transport Triggered Architecture

Transport triggered architecture (TTA) is one kind of application-specific instruction processors (ASIP), which fits embedded systems and offers a cost-effective trade-off between the energy-efficiency and performance. However its architecture and very long instruction word (VLIW) are alike, which also results in a very poor code density. In embedded systems, memory is one of the most expensive resources. Due to this, program code size has become one of the most critical design constraints. Code compression is one of the approaches to reduce the program code size; it results in smaller memories and reduced cost of the chip. In this paper, arithmetic coding is used to improve code density of TTA. Four DSP applications are used as benchmark applications and three processors based on TTA are tailored for each application. Finally arithmetic coding is applied to these applications and compression ratios obtained are compared with other code compression algorithms.