• DocumentCode
    2856344
  • Title

    Electromigration reliability comparison of Cu and Al interconnects

  • Author

    Alam, Syed M. ; Wei, Frank L. ; Gan, Chee Lip ; Thompson, Carl V. ; Troxel, Donald E.

  • fYear
    2005
  • fDate
    21-23 March 2005
  • Firstpage
    303
  • Lastpage
    308
  • Abstract
    Under similar test conditions, the electromigration reliability of Al and Cu metallization interconnect trees demonstrates significant differences because of the differences in interconnect architectural schemes. In Cu technology, the low critical stress for void nucleation at the interface of the Cu and the inter-level diffusion barrier, such as Si3N4, leads to asymmetric failure characteristics based on via position in a line. Unlike Al technology, a (jL) product filtering algorithm with a classification of separate via-above and via-below treatments is required for Cu interconnect trees. Using the best estimates of material parameters and an analytical model, we have compared electromigration lifetimes of Al and Cu dual-damascene interconnect lines. A reliability CAD tool, SysRel, has been used to simulate full-chip reliability of the same circuit layout with different interconnect technologies. In typical circuit operating conditions, Al bamboo lines have the best lifetime followed by Cu via-below, Cu via-above, and Al polygranular type lines.
  • Keywords
    diffusion barriers; electromigration; electronic design automation; integrated circuit interconnections; integrated circuit reliability; parameter estimation; trees (mathematics); Al; Cu; aluminium interconnects; analytical model; asymmetric failure characteristics; bamboo lines; copper interconnects; diffusion barrier; dual-damascene interconnect lines; electromigration reliability; full-chip reliability; interconnect architectural schemes; material parameter estimation; metallization interconnect trees; polygranular type lines; reliability CAD tool; via position; via-above lines; via-below lines; void nucleation; Classification tree analysis; Electromigration; Filtering algorithms; Integrated circuit interconnections; Life estimation; Lifetime estimation; Metallization; Parameter estimation; Stress; Testing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
  • Print_ISBN
    0-7695-2301-3
  • Type

    conf

  • DOI
    10.1109/ISQED.2005.51
  • Filename
    1410600