Title :
Low voltage test in place of fast clock in DDSI delay test
Author :
Yan, Haihua ; Xu, Gefu ; Singh, Adit D.
Author_Institution :
Dept. of Electr. & Comput. Eng., Auburn Univ., AL, USA
Abstract :
By testing the CUT at lower supply voltages, the CUT slows down and thus slow, low-cost testers can be used to perform DDSI (defect detection within slack intervals) tests. Apart from this, because the delay fault size is known in a DDSI test, this information can be further used to diagnose the causing mechanism behind the delay faults. Experimental results are presented to investigate the potential of the method.
Keywords :
delays; integrated circuit testing; deep sub-micron technology; defect detection within slack intervals test; delay fault size; delay test; low voltage test; Circuit faults; Circuit testing; Clocks; Delay effects; Design for testability; Fault detection; Low voltage; Performance evaluation; Pins; Signal generators; ATE; defect; delay test; low voltage test;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.75
