Title :
Realization of array architectures for video compression algorithms
Author :
Jehng, Yeu-Shen ; Chen, Liang-Gee ; Chiueh, Tzi-Dar ; Chen, Thou-Ho
Author_Institution :
Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
A practical design technique is presented to realize an array architecture for hierarchical block matching algorithms. A mapping procedure has been applied to derive the array processor from the algorithm. The proposed systolic array is derived to reduce the input/output bandwidth and the hardware cost. This systolic array is configured to be a single-chip of a cascaded architecture to match the requirements of real-time video applications
Keywords :
data compression; image coding; systolic arrays; array architectures; cascaded architecture; hardware cost; hierarchical block matching; input/output bandwidth; mapping procedure; real-time video applications; systolic array; video compression algorithms; Algorithm design and analysis; Bandwidth; Clocks; Computer architecture; Costs; Delay; Hardware; Motion estimation; Systolic arrays; Video compression;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230355
