The Design Methodology and Practice of Low Power SoC

With the evolution of the GSM mobile to a multi-media mobile terminal, optimizing the power consumption becomes an extremely complex task. New operating modes like the MP3 player mode or high resolution graphic games gain significant importance from a power consumption point-of-view. Submicron technologies with their significantly increased leakage currents pose another new challenge. New power concepts are required to achieve reasonable operating and standby times. The design methodology, power estimation and optimization of low power have to be pursued at all stages of the design down to gate level. They also have to be compatible with standard or custom software to minimize the impact on time-to-market for the custom product. This paper mainly talks about the lower power techniques implemented at system/architecture and register transfer level in a complex mix-signal mobile baseband SoC, low-power design optimization flow, power management technique fulfilling mobile application and on-chip low-power memory.