Title :
Analysis of the effect of LUT size on FPGA area and delay using theoretical derivations
Author :
Gao, Haixia ; Yang, Yintang ; Ma, Xiaohua ; Dong, Gang
Author_Institution :
Inst. of Microelectron., Xidian Univ., China
Abstract :
Based on architecture analysis of island-style FPGA, area and delay models of LUT FPGA are proposed. The effect of LUT size on FPGA area and performance is studied. Results show optimal LUT size conclusion from computation models is the same as that of experiments. A LUT size of 4 produces the best area results. A LUT size of 5 provides the better performance.
Keywords :
delays; field programmable gate arrays; logic design; table lookup; FPGA area; architecture analysis; delay; island-style FPGA; optimal LUT size; performance; Computational modeling; Computer architecture; Delay effects; Digital circuits; Field programmable gate arrays; Logic design; Microelectronics; Routing; Table lookup; Tiles;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.20
