A Simulator for Multi-Core Processor Micro-Architecture Featuring Inter-Core Communication, Power and Thermal Behavior

To effectively evaluate thermal behavior and inter-core communication on multi-core processors, we propose a simulation methodology and the corresponding implementation with runtime power and temperature calculation in this paper. The multi-core simulator is extended from our previous work, i.e. a heteromerous dual-core simulator. In our updated simulator, the well-established power model Wattch and a transient thermal simulation algorithm TILTS are integrated. The simulator is able to provide the runtime power and temperature metrics with little additional overhead compared with the original performance simulator. These results are illustrated with multimedia applications making use of all cores via inter-core communications. As far as we learn, we would like to highlight that our simulator is the first multi-core processor simulator based on SimpleScalar with thermal behavior and inter-core communication enabled. This simulator must be helpful for processor architects to make early decisions on thermal and performance trade-offs.