Title :
Optimizing large networks by repeated local optimization using a windowing scheme
Author :
Limqueco, Johnson Chan ; Muroga, Saburo
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
Describes a windowing scheme for optimizing large networks. Instead of actually breaking up a network into smaller, disjoint subnetworks, optimizing them separately, and then splicing them back together afterwards, the authors partition the network into overlapping regions and use a varying size window to sweep through these regions, each time making only the gates within a region visible to the logic optimizing algorithm, SYLON-REDUCE. To enhance opportunities for optimization, some partial don´t care information is considered for the outputs of each region. Using this scheme, considerable reduction in network size was achieved for several large multilevel benchmarks within a reasonable amount of time. The results were better than or comparable to existing logic optimizers such as MIS. The windowing scheme also allows effective timing optimization to be performed on large networks
Keywords :
circuit layout CAD; combinatorial circuits; logic CAD; SYLON-REDUCE; large networks; logic optimizing algorithm; multilevel benchmarks; network size; overlapping regions; partial don´t care information; repeated local optimization; timing optimization; varying size window; windowing scheme; Analytical models; Computer science; Logic; Merging; Partitioning algorithms; Splicing; Strontium; Timing;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230386