Analysis and design of LVTSCR-based EOS/ESD protection circuits for burn-in environment

Author

Semenov, O. ; Sarbishaei, H. ; Sachdev, M.

Author_Institution

Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada

fYear

2005

fDate

21-23 March 2005

Firstpage

427

Lastpage

432

Abstract

As technology feature size is reduced, ESD becomes one of the dominant failure modes due to the lower gate oxide breakdown voltage. Also, the holding voltage of LVTSCR devices is reduced with operating temperature increase. As a result, during stress testing (burn-in), the risk of latch-up in LVTSCR is extremely high. In this paper, a new latch-up free LVTSCR-based protection circuit is proposed. It can be reliably used in sub-0.18 μm CMOS technologies and burn-in environment. The proposed ESD circuit has higher holding voltage by 1.5× than the conventional LVTSCR structure at burn-in temperature. Under 3 kV HBM ESD stress, the developed LVTSCR-based protection circuit has the voltage peak less than the conventional LVTSCR structure and GG-MOSFET by 2× and 1.25×, respectively.

Keywords

CMOS logic circuits; electrostatic discharge; integrated circuit design; logic testing; 3 kV; EOS/ESD protection circuits; LVTSCR; burn-in environment; failure modes; gate oxide breakdown voltage; holding voltage; latch-up; operating temperature increase; stress testing; sub-0.18 μm CMOS technologies; CMOS technology; Circuit simulation; Earth Observing System; Electrostatic discharge; Ovens; Protection; Semiconductor diodes; Stress; Temperature; Voltage; Electrostatic discharge (ESD); LVTSCR; burn-in; electrical overstress (EOS); latch-up;

fLanguage

English

Publisher

ieee

Conference_Titel

Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on

Print_ISBN

0-7695-2301-3

Type

conf

DOI

10.1109/ISQED.2005.17

Filename

1410620