A floating point FIR filter with reduced exponent dynamic range

The authors present a new architecture for the realization of finite impulse response (FIR) digital filters with floating point coefficients. The approach exploits the characteristics of the envelope of many commonly encountered filter types to produce a structure which combines fixed point multipliers with a simple exponent processor based on differential coding. It is demonstrated that much of the response error improvement obtained through the employment of a floating point coefficient representation can be obtained by using this approach. In the case described, the differential exponents are limited to values of 0 or +1 and can thus be realized with a very simple hardware programmable shifter. The architecture is modular and suitable for VLSI implementation