Title :
Robust multi-level current-mode on-chip interconnect signaling in the presence of process variations
Author :
Venkatraman, Vishak ; Burleson, Wayne
Author_Institution :
Dept. of Electr. & Comput. Eng., Massachusetts Univ., Amherst, MA, USA
Abstract :
The paper presents a novel process-tolerant multi-level signaling system for on-chip interconnects. Novel multi-level driver and receiver designs are presented which are robust in the presence of process-induced parameter variation and uncertainties. Monte Carlo analyses show that the interconnect delay and total average power are normally distributed with a standard deviation of around 9.46% and 15.96% respectively for a 10 mm line in 100 nm technology. Individual parameter sensitivity analyses show that the total average power is most influenced by supply voltage and effective gate length, and delay is most influenced by interconnect resistance and capacitance. Yield of high performance and low power bins in 100 nm technology under process variations using the proposed multi-level signaling system is 36.1%, yield of high performance bins is 27.3% and yield of low power bins is 25.1% and yield of bad bins is only 11.5%.
Keywords :
Monte Carlo methods; capacitance; delays; driver circuits; electric resistance; integrated circuit design; integrated circuit interconnections; integrated circuit modelling; nanoelectronics; receivers; semiconductor process modelling; signalling; 10 mm; 100 nm; Monte Carlo analyses; average power; bad bins; effective gate length; high performance bins; interconnect capacitance; interconnect delay; interconnect models; interconnect resistance; low power bins; multilevel current-mode on-chip interconnect signaling; multilevel driver designs; multilevel receiver designs; multilevel signaling system; process technology models; process variations; process-tolerant signaling system; supply voltage; Communication system signaling; Delay; Monte Carlo methods; Power system interconnection; Robustness; Sensitivity analysis; Signal processing; System-on-a-chip; Uncertainty; Voltage;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.107