A method for identifying CMOS circuits with multiple DC operating points through topological criteria

The authors explore a general class of CMOS combinational circuits which can exhibit unintended multiple DC operating points, i.e. exhibit memory, with incorrect transistor sizing. Topological criteria are derived that can detect where such a problem might occur. For a specific circuit example, they examine the six-transistor (6-T) CMOS XOR gate. Circuit simulation using SPICE provided insight into the failure of the XOR gate to act like a logic gate in some cases and verified the topological criteria