Title :
A method for identifying CMOS circuits with multiple DC operating points through topological criteria
Author :
Landsberg, Paul ; Zukowski, Charles
Author_Institution :
Columbia Univ., New York, NY, USA
Abstract :
The authors explore a general class of CMOS combinational circuits which can exhibit unintended multiple DC operating points, i.e. exhibit memory, with incorrect transistor sizing. Topological criteria are derived that can detect where such a problem might occur. For a specific circuit example, they examine the six-transistor (6-T) CMOS XOR gate. Circuit simulation using SPICE provided insight into the failure of the XOR gate to act like a logic gate in some cases and verified the topological criteria
Keywords :
CMOS integrated circuits; SPICE; combinatorial circuits; integrated logic circuits; network topology; CMOS circuits; SPICE; XOR gate; combinational circuits; logic gate; multiple DC operating points; topological criteria; CMOS logic circuits; CMOS memory circuits; Circuit simulation; Combinational circuits; Latches; Logic circuits; Logic design; Logic gates; SPICE; Switches;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230426
