A prototype tool for optimum analog sizing using simulated annealing

Author

Medeiro-Hidalgo, F. ; Domínguez-Castro, R. ; Rodriguez-Vazquez, Angel ; Huertas, J.L.

Author_Institution

Dept. of Analog Design, Centro Nacional de Microelectron., Sevilla, Spain

Volume

4

fYear

1992

fDate

3-6 May 1992

Firstpage

1933

Abstract

A prototype tool is described which combines electrical simulation and statistical optimization for the automatic sizing of analog building blocks. A cost function structure is proposed to map a set of specification targets into a combinatorial optimization problem which was solved by statistical methods. The applicability of the tool is demonstrated via several examples. In particular, the design of the building blocks is considered for a 2 μm CMOS 16 b 20 kHz second-order sigma-delta modulator

Keywords

analogue circuits; circuit layout CAD; integrated circuit technology; linear integrated circuits; simulated annealing; statistical analysis; 2 micron; 20 kHz; CMOS; analog building blocks; automatic sizing; combinatorial optimization problem; cost function structure; optimum analog sizing; prototype tool; second-order sigma-delta modulator; simulated annealing; statistical methods; statistical optimization; Analog circuits; Circuit simulation; Cost function; Databases; Delta-sigma modulation; Design optimization; Equations; SPICE; Simulated annealing; Virtual prototyping;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0593-0

Type

conf

DOI

10.1109/ISCAS.1992.230431

Filename

230431