Title :
Design and analysis of area-IO DRAM/logic integration with system-in-a-package (SiP)
Author :
Wang, Anru ; Dai, Wayne
Author_Institution :
Dept. of Comput. Eng., California Univ., Santa Cruz, CA, USA
Abstract :
The paper presents a cost-effective area-IO DRAM (aDRAM)/logic integration implemented with CLC (chip-laminate-chip)-based system-in-a-package (SiP) technology. By inserting 512 area-IOs into the aDRAM, the bandwidth of the area-IO DRAM can achieve 10 GB/s when working under 166 MHz. An interface module with configurable IO width was also developed to make this implementation platform adoptable by various applications. A performance analysis, including bandwidth and power, is also presented. It is demonstrated that area-IO DRAM/logic integration with SiP technology provides a significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.
Keywords :
DRAM chips; integrated circuit design; integrated circuit packaging; integrated logic circuits; logic design; network analysis; semiconductor device packaging; 10 GB/s; SiP; area-IO DRAM/logic integration; chip-laminate-chip technology; embedded DRAM; off-chip DRAM; system-in-a-package; system-in-package; Logic design; Random access memory;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.38
