Design and analysis of area-IO DRAM/logic integration with system-in-a-package (SiP)

The paper presents a cost-effective area-IO DRAM (aDRAM)/logic integration implemented with CLC (chip-laminate-chip)-based system-in-a-package (SiP) technology. By inserting 512 area-IOs into the aDRAM, the bandwidth of the area-IO DRAM can achieve 10 GB/s when working under 166 MHz. An interface module with configurable IO width was also developed to make this implementation platform adoptable by various applications. A performance analysis, including bandwidth and power, is also presented. It is demonstrated that area-IO DRAM/logic integration with SiP technology provides a significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.