Title :
An I-IP based approach for the monitoring of NBTI effects in SoCs
Author :
Guardiani, C. ; Shibkov, A. ; Brambilla, A. ; Gajani, G. Storti ; Appello, D. ; Piazza, F. ; Bernardi, P.
Author_Institution :
Elite-DC S.r.l., Italy
Abstract :
In this paper we present a design for reliability methodology, with the goal of reducing the impact of transistor VTH degradation due for example to phenomena such as NBTI. It uses infrastructure IPs (I-IPs) featuring a self compensation scheme that automatically detects transistor aging effects and illustrates the design for test infrastructure used to make the SoC/System aware of the NBTI effects. This scheme is conceptually validated by using multi-level simulation and models. The discussion of possible exploitation models completes the paper.
Keywords :
monolithic integrated circuits; reliability; system-on-chip; transistors; I-IP based approach; NBTI effects; SoCs; multilevel simulation; negative bias temperature instability; reliability methodology; self compensation scheme; system aware; system-on-chip; test infrastructure; transistor aging effects; transistor degradation impact; Aging; CMOS technology; Degradation; Design methodology; Monitoring; Niobium compounds; Switching circuits; Timing; Titanium compounds; Very large scale integration; I-IPs; NBTI effects; SoC on-line monitoring;
Conference_Titel :
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International
Conference_Location :
Sesimbra, Lisbon
Print_ISBN :
978-1-4244-4596-7
Electronic_ISBN :
978-1-4244-4595-0
DOI :
10.1109/IOLTS.2009.5195977
