Using silicon contacts to test and burn-in flash memory, microprocessors, and FPGAs

The multichip module industry continues to see the cost of known-good die as an obstacle to growth. The use of chip scale packages has been proposed as a potential solution rather than bare die. However, some view the use of chip scale packages as a roadblock as well, due to the limited ability to make reliable cost-effective burn-in and test sockets for packages with ball pitches below 0.75 mm. By using Si as the temporary contact method for test and burn-in, Bear Technology has a solution to eliminate both barriers in the production of cost effective MCMs. Bear Technology has designed and manufactured Si contact sets for chip scale packages with pitches at or below 0.75 mm, along with known-good die carriers for high I/O microprocessors and field programmable gate arrays. These contact sets, mounted on ceramic or laminate interposers, plug into traditional industry test and burn-in sockets. With silicon as the temporary contact media, the fine pitch bumps on the die or chip scale package can be fanned out via a ceramic or laminate substrate to pitches of 1.27 mm or greater. This carrier can now use large pitch sockets to minimize board manufacturing cost and use of custom test and burn-in sockets. This paper outlines the steps necessary for the Si design, carrier design, and carrier assembly process, and demonstrates their use in applications including: flash memory chip scale packages, field programmable gate arrays (FPGA), and high I/O microprocessors. The specific die information along with the test and burn-in criteria is also presented