DocumentCode :
2857118
Title :
Efficient DFT Strategy for Complex Mixed-Signal SoC
Author :
Jian Hu ; Xubang Shen
Author_Institution :
Sch. of Comput. Sci. & Technol., Northwestern Polytech. Univ., Xi´an
fYear :
2008
fDate :
29-31 July 2008
Firstpage :
425
Lastpage :
430
Abstract :
With the improvement of integration capability and technology progress, there are much more challenges in the process of test development. The heterogeneous system formed by various of circuit structures and design styles makes test very difficult, and need more test time and test cost. This paper presents the DFT implementation for one communication baseband SoC. This mixed-signal baseband chip comprises analog and digital block, IP and embedded on-chip memory. To accommodate the requirement of test, using on-chip central test control unit could control all kinds of test mode of SoC, support traditional scan mode and scan-based delay test mode which orient to sub-micro technology, operating at different clock frequencies and domains, configurable on-chip MBIST and specific test modes, and other specific DFT techniques.
Keywords :
integrated circuit testing; mixed analogue-digital integrated circuits; system-on-chip; DFT strategy; embedded on-chip memory; heterogeneous system; mixed-signal SoC; mixed-signal baseband chip; on-chip central test control unit; sub-micro technology; Baseband; Circuit testing; Clocks; Costs; Delay; Design for testability; Electronic equipment testing; Logic testing; Random access memory; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Embedded Software and Systems Symposia, 2008. ICESS Symposia '08. International Conference on
Conference_Location :
Sichuan
Print_ISBN :
978-0-7695-3288-2
Type :
conf
DOI :
10.1109/ICESS.Symposia.2008.24
Filename :
4627198
Link To Document :
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