In-parallel maskless fabrication of nanowire-based device array

This paper reports simple and novel in-parallel fabrication processes of devices based in nanowires which avoid photolithography to pattern metallic electrodes. The wafer-level approaches allow low-risk device metallization of grown or deposited nanowire devices by selectively depositing evaporated metal on nanowire wafers. A silicon microstencil is thus used as hard mask defining the electrode regions. The absence of chemical-thermal processes during electrode fabrication dramatically reduces the risk of nanowire damage. Concept and development of the fabrication process is demonstrated on electrospun GaN and polymeric zinc choride (ZnCl2) nanowires wafers.