Title :
Floorplanning with consideration of white space resource distribution for repeater planning
Author :
Chen, Song ; Hong, Xianlong ; Dong, Sheqin ; Ma, Yuchun ; Cheng, Chung-Kuan
Author_Institution :
Dept. of Comput. Sci. & Technol., Tsinghua Univ., Beijing, China
Abstract :
In this paper, we proposed an effective and efficient model to evaluate the while space resource distribution in the floorplan/placement. The model discretizes the chip with a homogeneous rectangular mesh, in which the cost of each grid depends on the white space area and the routing congestion. The model has received application in our floorplanner to plan a good white space resource distribution to favor the later stage of repeater planning. On the other hand, non-zero area white-space blocks, which will join the formation of floorplan configurations, are introduced to adjust the amount and distribution of white space resources. Finally, a novel graph-based repeater assignment algorithm is devised to achieve the repeater planning. The number of nets failing to meet the repeater insertion constraint is reduced by 15.6 % on penalty of 2.2 % area usage reduction.
Keywords :
VLSI; industrial property; integrated circuit interconnections; integrated circuit layout; network routing; system-on-chip; IP blocks; SOC; VLSI; floorplanner; floorplanning; graph-based repeater assignment algorithm; homogeneous rectangular mesh; nonzero area white-space blocks; repeater planning; routing congestion; white space resource distribution; Computer science; Costs; Delay; Repeaters; Resource management; Routing; Space technology; Technology planning; Very large scale integration; White spaces;
Conference_Titel :
Quality of Electronic Design, 2005. ISQED 2005. Sixth International Symposium on
Print_ISBN :
0-7695-2301-3
DOI :
10.1109/ISQED.2005.58