Title :
Designing dependable multicore system with unreliable components
Author_Institution :
ARM R&D, USA
Abstract :
Single core chip architecture do not scale well due to various design and reliability challenges. Multicore system with large numbers of cores are becoming common to take advantage of Moore´s law. However, there exist various reliability concerns in nanoscale era due to spatial, temporal and dynamic variations. The only way to enable sustained scaling of multicore systems is to make the architecture robust by using adaptive design techniques and having redundant cores which can replace faulty ones.
Keywords :
CMOS integrated circuits; integrated circuit design; integrated circuit reliability; Moore´s law; adaptive design techniques; dependable multicore system; dynamic variation; reliability; single core chip architecture; spatial variation; temporal variation; Built-in self-test; CMOS technology; Circuit faults; Error correction; Moore´s Law; Multicore processing; Power system reliability; Redundancy; Robustness; Timing;
Conference_Titel :
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International
Conference_Location :
Sesimbra, Lisbon
Print_ISBN :
978-1-4244-4596-7
Electronic_ISBN :
978-1-4244-4595-0
DOI :
10.1109/IOLTS.2009.5195999
