Title :
A fault tolerant journalized stack processor architecture
Author :
Ramazani, Abbas ; Amin, Mohsin ; Monteiro, Fabrice ; Diou, Camille ; Dandache, Abbas
Author_Institution :
LICM Lab., Univ. Paul Verlaine, Metz, France
Abstract :
Dependable architectures play an important role in many areas that impact our lives. Dependability is achieved by using a set of analysis and design techniques that increases the complexity and consequently the cost of systems. In this paper, to meet low cost requirement of IP cores, we propose a simple dependable stack processor architecture using a re-execution model of instructions in the case of error detection in consecutive sequences of instructions execution. The architecture is based on applying two memory journals as intermediate stages between processor and main memory in write operations. Then, we present the results obtained by using the developed emulation tools.
Keywords :
error detection; fault tolerant computing; memory architecture; multiprocessing systems; IP cores; dependability; error detection; fault tolerance; instruction execution sequences; memory journals; re-execution model; stack processor architecture; Costs; Design methodology; Emulation; Fault tolerance; Laboratories; Logic; Protection; Registers; Software safety; System-on-a-chip;
Conference_Titel :
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International
Conference_Location :
Sesimbra, Lisbon
Print_ISBN :
978-1-4244-4596-7
Electronic_ISBN :
978-1-4244-4595-0
DOI :
10.1109/IOLTS.2009.5196013
