An Input Vector Monitoring Concurrent BIST scheme exploiting “X” values

Input Vector Monitoring Concurrent Built-In Self Test schemes provide the capability to perform testing while the Circuit Under Test operates normally, by exploiting vectors that appear at the inputs of the CUT during its normal operation. The Concurrent Test Latency of an input vector monitoring scheme is the time required for the concurrent test to complete. Input Vector Monitoring Concurrent BIST schemes that have been proposed to date, are based mainly on test sets containing binary (1 or 0) values. Test sets extracted by modern CAD tools, largely contain don´t care (dasiaXpsila) values. In this work a novel input vector monitoring concurrent BIST scheme is presented, based on a test set containing dasiaXpsila values. The proposed scheme compares favourably with respect to the hardware overhead - concurrent test latency trade off with previously proposed techniques.