A new VLSI algorithm for high throughput image filtering

A new algorithm for the multiplication-accumulation process, suitable for high throughput image filtering operation, is proposed. This algorithm exploits a-priori knowledge of not only the zero elements of a filter mask, but also that of the zero-bit positions in each of its non-zero elements as well. This results in a throughput which is higher than other algorithms for multiplication-accumulation used in image filtering. The VLSI architecture realizing the new algorithm is also proposed. Experimental results are provided considering a 5×5 filter mask. The results indicate 49% reduction in computation time while filtering a 512×512 pixel picture frame. This reduction was achieved without any additional requirement of the VLSI layout area for logic gates