DocumentCode
2857765
Title
C-testable S-box implementation for secure advanced encryption standard
Author
Rahaman, H. ; Mathew, J. ; Jabir, A. ; Pradhan, D.K.
Author_Institution
Dept. of Comput. Sci., Univ. of Bristol, Bristol, UK
fYear
2009
fDate
24-26 June 2009
Firstpage
210
Lastpage
211
Abstract
We propose a C-testable S-box implementation which is one of the most complex blocks in AES hardware implementation. Only 12 constant vectors are sufficient to achieve 100% fault coverage in the S-box. C-testability is achieved with an extra hardware overhead of 8.2 percent.
Keywords
cryptography; integrated circuit testing; integrated logic circuits; logic gates; AES algorithm; C-testable design; EXOR gate; EXOR tree; S-BOX architecture; extra hardware overhead; iterative algorithm; secure advanced encryption standard; substitution table; Circuit faults; Circuit testing; Computer science; Controllability; Cryptography; Design for testability; Galois fields; Hardware; Information security; Iterative algorithms;
fLanguage
English
Publisher
ieee
Conference_Titel
On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International
Conference_Location
Sesimbra, Lisbon
Print_ISBN
978-1-4244-4596-7
Electronic_ISBN
978-1-4244-4595-0
Type
conf
DOI
10.1109/IOLTS.2009.5196017
Filename
5196017
Link To Document