A low-cost fault-tolerant technique for Carry Look-Ahead adder

Author

Namazi, Alireza ; Sedaghat, Yasser ; Miremadi, Seyed Ghassem ; Ejlali, Alireza

Author_Institution

Dept. of Comput. Eng., Sharif Univ. of Technol., Tehran, Iran

fYear

2009

fDate

24-26 June 2009

Firstpage

217

Lastpage

222

Abstract

This paper proposes a low-cost fault-tolerant Carry Look-Ahead (CLA) adder which consumes much less power and area overheads in comparison with other fault-tolerant CLA adders. Analytical and experimental results show that this adder corrects all single-bit and multiple-bit transient faults. The Power-Delay Product (PDP) and area overheads of this technique are decreased at least 82% and 71%, respectively, as compared to adders which use traditional TMR, parity prediction, and duplication techniques.

Keywords

adders; carry logic; circuit testing; fault tolerance; TMR; area overheads; carry look-ahead adder; duplication; low-cost fault-tolerant technique; multiple-bit transient faults; parity prediction; power-delay product; single-bit transient faults; triple modular redundancy; Adders; Arithmetic; Circuit faults; Electrical fault detection; Error correction; Fault detection; Fault tolerance; Fault tolerant systems; Redundancy; Very large scale integration; Carry Look-Ahead Adder; Fault Tolerance; Single-Event Transient;

fLanguage

English

Publisher

ieee

Conference_Titel

On-Line Testing Symposium, 2009. IOLTS 2009. 15th IEEE International

Conference_Location

Sesimbra, Lisbon

Print_ISBN

978-1-4244-4596-7

Electronic_ISBN

978-1-4244-4595-0

Type

conf

DOI

10.1109/IOLTS.2009.5196019

Filename

5196019