Delay-fault tolerance to power supply Voltage disturbances analysis in nanometer technologies

In nanometer technologies, as variability is becoming one of the leading causes for chip failures, signal integrity is a key issue for high-performance digital System-on-Chip (SoC) products. In this paper, analysis is focused on the occurrence of Delay-faults due to Power-supply disturbances in nanometer technologies. Using a previously proposed VT (power supply Voltage and Temperature)-aware time management methodology, it is shown that nanometer technologies impose the need of fault-tolerance methodologies, although the margins of tolerance or fault-free operations are being reduced as technology scales down. SPICE simulation results with 350 nm, 130 nm, 90 nm, 65 nm, 45 nm and 32 nm CMOS technologies show an increasing dependence of propagation delays on power supply variations, as technology is being scaled down. Monte Carlo simulations show that, even in the presence of process variations, a dynamic delay-fault tolerance methodology can be rewarding even at nanometer scale, although the margins for Power-supply variations are becoming smaller.