Title :
YAWARA: A Meta-Level Optimizing Computer System
Author :
Baba, Takanobu ; Yokota, Takashi ; Ootsu, Kanemitsu ; Furukawa, Fumihito ; Ishihara, Gaku ; Saito, Moriyuki
Author_Institution :
Dept. of Inf. Sci., Utsunomiya Univ., Tochigi
Abstract :
This paper proposes a new, autonomous and dynamic optimization framework, called a meta-level computation. In this framework, a meta-level processor acquires the execution profile of a base-level processor, i.e. a conventional von Neumann machine, produces the optimized base-level configuration and performs the reconfiguration. We define the meta-level computation model based on the considerations of hardware versus software reconfiguration, static versus dynamic reconfiguration and homogeneous versus heterogeneous architecture. The model employs a thread-level reconfiguration to realize the autonomous and dynamic optimization on a uniformly structured multiprocessor. As an implementation of the computation model, we propose a software/hardware combined system, called the YAWARA system. The software system realizes both static and dynamic feedback-directed, autonomous optimization. The hardware system consists of thread engines, each of which includes hardware mechanisms for profiling and feedback-directed resource control
Keywords :
instruction sets; microprocessor chips; multi-threading; multiprocessing systems; parallel architectures; YAWARA; autonomous optimization; dynamic optimization; dynamic reconfiguration; feedback-directed resource control; hardware mechanisms; hardware reconfiguration; hardware system; heterogeneous architecture; homogeneous architecture; meta-level optimizing computer system; multiprocessor; profiling control; software reconfiguration; software system; static reconfiguration; thread engines; thread-level reconfiguration; von Neumann machine; Computational modeling; Computer aided instruction; Computer architecture; Control systems; Hardware; Information science; Laboratories; Software systems; Transistors; Yarn;
Conference_Titel :
Innovative Architecture for Future Generation High-Performance Processors and Systems, 2004. Proceedings
Conference_Location :
Maui, HI
Print_ISBN :
0-7695-2205-X
DOI :
10.1109/IWIA.2004.10007