An overview of Altera SDK for OpenCL: A user perspective

In recent years there has been a great interest in High Level Synthesis (HLS) CAD tools to raise the level of design abstraction, reduce design time, rapidly explore the design space and fully exploit the multi-million gate heterogeneous hardware platforms provided by dramatic improvements in integrated circuits. Open Computing Language (OpenCL) is a well-known standard for heterogeneous computing. The Altera SDK for OpenCL is used to convert OpenCL code to kernels that can be run on an FPGA accelerator card. It is a recently introduced HLS CAD tool that allows for the potential to convert existing, or create new C/C++ programs that utilize dedicated hardware to execute specific applications much faster and more efficient than current computer systems, whether single core or multi-core. This can all be done without the knowledge of FPGAs, VHDL, or Verilog as the SDK converts the OpenCL files into Verilog models that are then compiled into FPGA hardware. This paper presents a user-centric overview of Altera SDK for OpenCL. As a first step to achieve the best speedup, the candidate algorithm for acceleration must be analyzed to check if it is inherently parallelizable. The key features such as designing appropriate OpenCL kernels and host program, their compilation, execution and testing are summarized. A working example for accelerating a simple matrix multiplication algorithm is described. Our motivation is to provide the novice users with a useful tutorial that will enable them to quickly become proficient in using this important HLS CAD tool. To our knowledge, such a user-centric tutorial has not been presented so far in the literature.