Title :
A fast parallel multiplier architecture
Author :
Hekstra, G.J. ; Nouta, R.
Author_Institution :
Dept. of Electr. Eng., Delft Univ. of Technol., Netherlands
Abstract :
A parallel multiplier architecture is presented that is both fast and small and a viable alternative to the array and tree type multipliers. The speed of this architecture is close to that of the binary and Wallace tree architectures for common sizes of multipliers, while the area is only marginally larger than that of the array multiplier. The structure of the architecture is very regular, making it ideal for automatic generation. The internal structure of this floorplan can be generated very easily from a set of seven VLSI leafcells requiring no extra routing
Keywords :
CMOS integrated circuits; circuit layout CAD; integrated logic circuits; multiplying circuits; parallel architectures; CMOS double metal sea of gates fish bone image; VLSI leafcells; automatic generation; floorplan; internal structure; parallel multiplier architecture; Area measurement; Arithmetic; Bismuth; Delay; Paper technology; Routing; Silicon; Size measurement; Very large scale integration; Wiring;
Conference_Titel :
Circuits and Systems, 1992. ISCAS '92. Proceedings., 1992 IEEE International Symposium on
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0593-0
DOI :
10.1109/ISCAS.1992.230572
