Fast optimal algorithm for the CMOS functional cell layout based on transistor reordering

The authors propose a fast optimal algorithm for CMOS functional cell layout. The algorithm takes a logic function or a circuit schematic for the input, and outputs a optimal gate sequence for the cell permitting the transistor reordering. Here the constructive approach and a new idea, reordering-based operations, are introduced. Considering the connections of only 18 types of dual trails, the optimal solution was obtained faster than the best algorithm published so far. In some cases, the time complexity is linear to the number of the transistors. For practical cases the expected time complexity is estimated as almost linear