Title :
Parallelism in structural fault testing of embedded cores
Author :
Nourani, M. ; Papachristou, C.
Author_Institution :
Dept. of Electr. & Comput. Eng., Tehran Univ., Iran
Abstract :
We present a global design for test methodology for testing a core-based system in its entirety. This is achieved by introducing a “bypass” mode for each core by which the data can be transferred from a core input port to the output port without interfering the core circuitry itself. The interconnections are thoroughly tested since they are used to propagate test data (patterns or signatures) in the system. The system is modeled as a directed weighted graph in which the core accessibility is solved as a shortest path problem
Keywords :
built-in self test; design for testability; fault diagnosis; integrated circuit testing; logic testing; parallel processing; core accessibility; core input port; data transfer; embedded cores; global design; graph modelling; input output test path; interconnections; path characteristic function; shortest path problem; structural fault testing; structural testing; test data; test methodology; Built-in self-test; Circuit faults; Circuit testing; Design methodology; Integrated circuit interconnections; Logic testing; Protection; Semiconductor device testing; System testing; System-on-a-chip;
Conference_Titel :
VLSI Test Symposium, 1998. Proceedings. 16th IEEE
Conference_Location :
Monterey, CA
Print_ISBN :
0-8186-8436-4
DOI :
10.1109/VTEST.1998.670843
