DocumentCode
2858659
Title
A precision trim technique for monolithic analog circuits
Author
Erdi, G.
Author_Institution
Precision Monolithics, Inc., Santa Clara, CA, USA
Volume
XVIII
fYear
1975
fDate
27426
Firstpage
192
Lastpage
193
Abstract
A precision shortable diode trim design applied at the wafer test phase, will be described, citing adjustment of op-amp offset to 2.5 μV and drifts to less than 0.6 μV/°C.
Keywords
Analog circuits; Circuit noise; Circuit testing; Equivalent circuits; Instruments; Operational amplifiers; Semiconductor diodes; Temperature; Voltage; Zinc;
fLanguage
English
Publisher
ieee
Conference_Titel
Solid-State Circuits Conference. Digest of Technical Papers. 1975 IEEE International
Type
conf
DOI
10.1109/ISSCC.1975.1155393
Filename
1155393
Link To Document